Many applications in modern electronics require that discrete-time signals, generated using computers and digital signal processors, be converted to linear (analog) signals, e.g., for transmission as electromagnetic signals. Typically, this transformation is made using a conventional digital-to-analog converter (DAC). However, the present inventor has discovered that each of the presently existing converters exhibits shortcomings that limit overall performance at very high sample rates.
Due to parallel processing and other innovations, the digital information processing bandwidth of computers and signal processors has advanced beyond the capabilities of state-of-the art DACs. Therefore, converters with higher instantaneous bandwidth are desired. Existing solutions are limited by instantaneous bandwidth (sample rate), effective conversion resolution (accuracy), or both.
The resolution of a DAC is a measure of the precision with which a quantized signal can be transformed into a continuous-time continuously variable signal, and typically is specified as a ratio of the total signal power to the total noise plus distortion power at the DAC output. This signal-to-noise-and-distortion ratio (SNDR) of a DAC is commonly expressed on a logarithmic scale in units of decibels (dB). When a discrete-time discretely variable (digital) signal is converted into a continuous-time continuously variable (analog) signal, the quality of the analog signal is corrupted by various limitations and errors introduced during the conversion process. Examples include: 1) the finite granularity of the DAC digital inputs (bit width) that produces quantization noise; 2) the imprecise (e.g., nonlinear) mapping of digital inputs to corresponding discrete output voltage or current levels that introduces distortion in the form of rounding inaccuracies (rounding errors); 3) the imperfect timing between transitions in output voltages or currents relative to transitions in digital inputs that causes noise in the form of sampling jitter; and 4) the thermal noise associated with active devices (e.g., switches and amplifiers) that couples onto the DAC output. High-resolution converters transform discrete signals into continuously variable signals using a rounding operation with finer granularity and more linear mapping of digital inputs to output voltage and current. Instantaneous conversion bandwidth is limited by the Nyquist criterion to a theoretical maximum of one-half the converter sample rate (the Nyquist limit). However, high-resolution conversion (of >10 bits) conventionally has been limited to instantaneous bandwidths of about a few gigahertz (GHz) or less.
Converters that quantize signals at a sample rate (fS) that is at or slightly above a frequency equal to twice the signal bandwidth (fB) with several or many bits of resolution are conventionally known as Nyquist-rate converters. Prior-art Nyquist-rate converter architectures include those implemented using resistor ladder networks (e.g., R-2R networks), or those employing switched current/voltage sources with unary (i.e., equal) weighting or binary weighting. A conventional resistor-ladder DAC, such as that shown in FIG. 1A, generates a variable output voltage equal to the binary-weighted sum of multiple, two-level (i.e., digital) inputs. The voltage summation operation is performed using a network of resistors, having appropriately weighted resistance (i.e., a binary-weighted resistor ladder). The voltage at the resistor network output sometimes is buffered and/or sometimes is smoothed, using an analog lowpass filter, to produce a continuously variable signal. An alternative DAC structure is illustrated in FIG. 1B, which instead of a resistor ladder network, uses a switched bank of current sources to generate a variable output current equal to the binary-weighted sum of digital inputs. As shown in FIG. 1B, the output current sometimes is converted to a proportional output voltage using a transimpedance amplifier (i.e., a current-to-voltage converter).
Conventional Nyquist converters potentially can achieve very high instantaneous bandwidths, but as discussed in greater detail below, the present inventor has discovered that component mismatches in the resistor ladder network, or in the switched current sources, can introduce rounding errors that significantly limit attainable resolution. In addition, the resolution of conventional Nyquist converters is limited by other practical implementation impairments such as sampling jitter and thermal noise. Although Nyquist converters potentially could realize high resolution at instantaneous bandwidths greater than 10 GHz in theory, due to the foregoing problems, this potential has been unrealized in conventional Nyquist converters.
A conventional approach that attempts to reduce quantization noise and errors uses an oversampling technique. A conventional Nyquist converter transforms each digital input into a single proportional output sample (i.e., voltage or current). Conventional oversampling converters first transform each digital input into a sequence of pseudorandom, two-valued samples (i.e., a positive value or a negative value), such that the average of this two-valued, pseudorandom sequence is proportional to the digital input. Therefore, oversampling converters generate coarse (e.g., two-level) analog voltage or current outputs at a rate (i.e., fS) that is much higher than twice the input signal bandwidth (i.e., fS>>fB), where N=fS/fB/2 is conventionally referred to as the oversampling ratio of the converter. A continuously variable output that is proportional to the digital inputs is produced from the two-valued, pseudorandom output sequence using a lowpass filtering operation that effectively averages the output samples. Although this averaging process reduces the bandwidth of the oversampling converter, it has the benefit of improving the converter resolution by mitigating quantization noise (i.e., the noise introduced by using only two values to represent a continuously variable signal) and errors resulting from component mismatches, sampling jitter, and thermal noise. The extent of this benefit is directly related to the output sample rate fS (i.e., benefit increases as sample rate increases) and is conventionally enhanced using oversampling in conjunction with an operation referred to as noise shaping, that ideally attenuates quantization noise and errors in the signal bandwidth without also attenuating the signal itself. Through this noise-shaped quantization operation and subsequent lowpass filtering (i.e., output averaging), oversampling converters transform a high-rate intermediate signal having low resolution into a relatively low bandwidth output signal having improved resolution.
FIGS. 2A&B illustrate block diagrams of conventional, lowpass oversampling converters 5A and 5B, respectively. A conventional oversampling converter will typically employ an upsampling operation 6, generally consisting of upsampling 6A by the converter oversampling ratio N followed by interpolation (lowpass) filtering 6B, and uses delta-sigma (ΔΣ) modulation 7A&B to shape quantization noise. As the name implies, delta-sigma modulators 7A&B shape the noise that will be introduced by two-level quantizer 10 via difference operation 8 (i.e., delta) and integration operation 13 (i.e., sigma), e.g.,
      I    ⁡          (      z      )        =            1              1        -                  z                      -            1                                .  The converter 5A, shown in FIG. 2A, uses what is conventionally referred to as an interpolative ΔΣ modulator circuit (i.e., circuit 7A). Circuit 5B uses an alternative ΔΣ modulator 7B, which has the error-feedback structure shown in FIG. 2B. See D. Anastassiou, “Error Diffusion Coding in A/D Conversion,” IEEE Transactions on Circuits and Systems, Vol. 36, 1989. Generally speaking, the delta-sigma modulator processes the signal with one transfer function (i.e., the signal transfer function or STF) and the quantization noise with a different transfer function (i.e., the noise transfer function or NTF). Conventional transfer functions (i.e., after accounting for the implicit delay of the clocking operation on two-level quantizer 10) are of the form STF (z)=z−k and NTF(z)=(1−z−1)P, where k is an integer, z−1 represents a unit delay equal to TCLK=1/fCLK, and P is called the order of the lowpass modulator or noise-shaped response. Converter circuits 5A&B employ first-order ΔΣ modulation (i.e., P=1) that produces STF frequency response 30 and NTF frequency response 32 that are shown in FIG. 2C. For both circuits 5A&B, the output sample rate fS, and therefore the converter oversampling ratio N, is determined by the clock frequency fCLK of the delta-sigma modulator 7A&B (i.e., shown as the input clock to the two-level quantizer 10 in FIGS. 2A&B), such that fS=fCLK.
For a given converter resolution, the bandwidth of a conventional oversampling converter typically is increased by increasing the clock frequency fCLK of the ΔΣ modulator, thereby making the oversampling ratio N higher. Similarly, for a given bandwidth, higher oversampling ratios N result in improved converter resolution. Generally speaking, the present inventor has determined that the resolution B of a conventional oversampling converter is given by
      B    =                  Δ        ⁢                                  ⁢        Q            -                        1          2                ·                              log            2                    ⁡                      (                                          ∫                0                                                      f                    s                                    /                  2                                            ⁢                              ❘                                                                            NTF                      ⁡                                              (                                                                              ⅇ                                                          2                              ⁢                              πj                              ⁢                                                                                                                          ⁢                              fT                                                                                ,                          P                                                )                                                              ·                                          F                      ⁡                                              (                                                  ⅇ                                                      2                            ⁢                            πj                            ⁢                                                                                                                  ⁢                            fT                                                                          )                                                                              ⁢                                      ❘                    2                                    ⁢                                                                          ⁢                                      ⅆ                    f                                                                        )                                ,where ΔQ is the number of bits at the output of quantization circuit 10 (i.e., level of coarse quantization which typically is equal to one) and F(e2πjfT) is the frequency response of output filter 12. Increasing the clock frequency fCLK of the ΔΣ modulator requires circuitry with higher speed capability, and generally, higher power dissipation. Alternatively, higher bandwidth and/or improved resolution are realized by increasing the order P of the ΔΣ modulator. Compared to converter circuits 5A&B, lowpass oversampling converter 5C, illustrated in FIG. 2D, realizes higher bandwidth (or improved resolution) using interpolative ΔΣ modulator circuit 7C, which incorporates two integration operations (i.e., circuits 13A&B) to produce a noise-shaped response that is second-order (i.e., P=2). Increasing modulator order P, however, causes undesirable reductions in the stability of the modulator. The present inventor has discovered, for example, that a ΔΣ modulator of order four or higher is unstable with two-level (i.e., ΔQ=1) quantization. The present inventor also has discovered that the multi-level quantization circuits needed to stabilize high-order modulators introduce rounding errors that are not subjected to the noise-shaped response of the ΔΣ modulator. As a result of constraints on the operating speed of conventional ΔΣ modulator circuits and on the rounding accuracy of multi-level quantization circuits, increasing the clock frequency and/or the order of the ΔΣ modulator has limited utility in improving the bandwidth and/or resolution of conventional oversampling converters.
The delta-sigma converters 5A-C illustrated in FIGS. 2A,B&D are conventionally known as lowpass, delta-sigma converters. A variation on the conventional lowpass converter employs bandpass delta-sigma modulation to allow conversion of narrowband signals that are centered at frequencies other than zero. An exemplary bandpass oversampling converter 40A, illustrated in FIG. 3A, includes a bandpass delta-sigma modulator 42 that shapes noise from two-level quantizer 10 by performing a difference operation 8 (i.e., delta) and an integration operation 14 (i.e., sigma), respectively, where
      H    ⁡          (      z      )        =            z              -        1                    1      +              z                  -          2                    and z−1 represents a unit delay equal to TCLK. After accounting for the implicit delay of the clocking operation on two-level quantizer 10, conventional bandpass ΔΣ modulator 42 has a STF(z)=z−1 and a second-order NTF(z)=1−z−2. Like converter circuits 5A&C, bandpass oversampling converter circuit 40A is an interpolative structure that produces a signal response 70, shown in FIG. 3B, that is different from its quantization noise response 71. As shown in FIG. 3B, the bandpass modulator of FIG. 3A has a NTF with a minimum 72 at the center of the converter Nyquist bandwidth (i.e., ¼·fS). Producing an NTF with a spectral null at a frequency other than zero hertz requires a real ΔΣ modulator with, at minimum, a second-order response (i.e., the delay operator z is raised to a power of −2), and in general, the NTF of a bandpass ΔΣ modulator is of the form (1+ρ·z−1+z−2)P, where −2≦ρ≦+2. Although the signal response 70 of circuit 40A is all-pass, the present inventor has discovered that, in general, the STF of bandpass oversampling converters is not all-pass when interpolative modulator structures are employed. Conversely, the present inventor has discovered that bandpass oversampling converters that utilize the alternative error-feedback structure of FIG. 2B, have an STF which is uniformly all-pass. After two-level quantization 10, bandpass filtering 43 of quantization noise, similar to that performed in the standard conventional lowpass oversampling converter (e.g., either of converters 5A&B) is performed. In FIG. 3A, it is assumed that the input data (i.e., digital input) rate is equal to the converter output sample rate fCLK, and therefore, an upsampling operation is not included. However, in cases where the input data rate is lower than the converter output sample rate fCLK, an upsampling operation would be included.
Although oversampling with noise-shaped quantization can reduce quantization noise and other conversion errors, the output filtering (i.e., smoothing) operations generally limit the utility of oversampling converters to applications requiring only low instantaneous bandwidth. Conventional schemes for overcoming the bandwidth and resolution performance limitations of data converters generally have been devised with a focus on the conversion of analog signals to digital signals (i.e., analog-to-digital conversion), rather than on the conversion of digital (discrete) signals to analog (linear) signals (i.e., digital-to-analog conversion), which is the subject of the present invention. The present inventor has discovered that these conventional schemes for improving bandwidth and/or resolution in analog-to-digital conversion suffer from significant disadvantages, particularly in attempts to directly adapt these schemes for use in digital-to-analog conversion applications.
For example, one attempt to overcome the instantaneous bandwidth limitations of high-resolution, analog-to-digital (A/D) converters is conventional hybrid filter bank (HFB) converter 50, illustrated in FIG. 4A. See A. Petraglia and S. K. Mitra, “High Speed A/D Conversion Using QMF Banks,” Proceedings: IEEE Symposium on Circuits and Systems, 1990. A conventional HFB converter consists of multiple narrowband converters that are operated in parallel, such that: 1) a wideband, analog signal is spectrally decomposed into multiple narrowband segments (i.e., sub-bands), using an array of analog bandpass filters (i.e., analysis filters 52A-C) with minimally overlapped frequency responses; 2) each sub-band is downconverted (i.e., downsampler 53) and digitized using low-speed converter 54; and 3) the digitized outputs of each converter 54 are upconverted (i.e., upsampler 56) and then combined, using an array of digital bandpass filters (i.e., synthesis filters 58A-C) with frequency responses that overlap to create an overall response that is all-pass (i.e., digital filters with near-perfect signal reconstruction properties). For the conversion of digital signals into analog signals, the present inventor has contemplated a complementary scheme, where by direct adaptation: 1) analog analysis filters 52A-C at the converter input are moved to the converter output and become signal synthesis filters; 2) analog-to-digital converters 54 are replaced with digital-to-analog converters; and 3) digital synthesis filters 58A-C are moved to the converter input and become signal analysis filters. However, the present inventor has discovered that the performance of this complementary scheme is limited by the intermodulation distortion (i.e., intermodulation or non-ideal cross-products) of the analog mixers needed for the analog upconversion operation. The present inventor has also discovered that at high sample rates (e.g., greater than several gigahertz), the complexity of multiple digital analysis filters (i.e., one per processing branch) can be prohibitive in many applications, such as those where more than just a few parallel processing branches are needed to realize desired conversion bandwidth and resolution performance.
A second attempt to overcome the instantaneous bandwidth limitations of high-resolution, analog-to-digital (A/D) converters is conventional Multi-Band Delta-Sigma (MBΔΣ) converter 70, shown in FIG. 4B. See Aziz, P., “Multi Band Sigma Delta Analog to Digital Conversion”, IEEE International Conference on Acoustics, Speech, and Signal Processing, 1994. The conventional MBΔΣ approach is similar to the conventional HFB approach except that use of bandpass ΔΣ converters, instead of lowpass A/D converters, eliminates the need for analog analysis filters (e.g., filters 52A-C of circuit 50 in FIG. 4A), downconversion operations (e.g., downsampler 53 of circuit 50 in FIG. 4A), and upconversion operations (e.g., upsampler 56 of circuit 50 in FIG. 4A). For converting digital signals to analog signals, the present inventor has contemplated a complementary scheme in which by direct adaptation: 1) analog ΔΣ modulators 72 are replaced with equivalent digital ΔΣ modulators; and 2) digital synthesis filters 73A-C are replaced with equivalent analog synthesis filters. The present inventor, however, has discovered that the sampling rate (i.e., oversampling ratio) of this complementary scheme is limited by the switching times (speed) of the digital logic needed to implement the digital ΔΣ modulators (i.e., a less significant limitation in analog implementations). Furthermore, the present inventor also has discovered that this complementary scheme is impractical because it requires a bank of continuous-time analog filters whose individual responses replicate those of high-order, digital filters with perfect reconstruction properties (i.e., a bank of filters with an overall response that is all-pass). Unlike the HFB approach of FIG. 4A, where imperfections in the analog filter bank are mitigated by increasing the complexity of the associated digital filter bank (see S. R. Velazquez, T. Q. Nguyen, and S. R. Broadstone, “Design of Hybrid Filter Banks for Analog/Digital Conversion,” IEEE Transactions on Signal Processing, 1998), the conventional MBΔΣ approach provides no means of compensating for the amplitude and group delay distortion introduced by analog filter banks with imperfect signal reconstruction properties. Use of direct digital-to-analog filter transformations (i.e., those based on conventional bilinear or impulse-invariant transforms) to design analog filter banks with an all-pass response, generally results in analog filters of unmanageable complexity (i.e., filter orders of 30 or more). Approximations to these direct transformations conventionally support only a small number of parallel processing paths (e.g., see A. Fernandez-Vazquez and G. Jovanovic-Dolecek, “Design of Real and Complex Linear-Phase IIR Modified QMF Banks,” IEEE Asia Pacific Conference on Circuits and Systems, 2006), and/or require circuits that are not practical for operation at multi-gigahertz sample rates, such as switched-capacitor or other impractical circuits (e.g., see P. C. R. Brandao and A. Petraglia, “A Switched-Capacitor Hadamard Filter Bank in 0.35 μm CMOS,” Proceedings: 48th Midwest Symposium on Circuits and Systems, 2005; P. M. Furth and A. G. Andreou, “A Design Framework for Low Power Analog Filter Banks”, IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications, 1995). As discussed in greater detail below, however, the present inventor has discovered that with relatively minor modifications to standard filter responses (e.g., only center frequency, bandwidth, and/or order), the residual amplitude and group delay distortion introduced by the analog filter bank can be reduced to levels that are acceptable in many applications.
In addition to the conventional frequency-interleaved schemes employed by converters 50 and 70 (i.e., schemes involving spectral decomposition of the converter input signal), another attempt at overcoming the instantaneous bandwidth limitations of high-resolution, analog-to-digital converters involves the use of conventional time-interleaving to increase the bandwidth, or equivalently, the sample rate of a ΔΣ modulator. Circuits 80A&B, which are illustrated in FIGS. 5A&B, respectively, are conventional time-interleaved ΔΣ modulators that employ a time-interleaving factor of m=2 (i.e., two parallel processing paths). Conventional time-interleaved ΔΣ modulators, such as circuits 80A&B, are interpolative structures wherein the integrator function (i.e., integrator 13 of circuit 80A and integrators 13A&B of circuit 80B) is performed by circuits that operate in parallel. This process of implementing a particular processing function using parallel circuits is sometimes referred to in the prior art as polyphase decomposition, or multirate processing. In circuits 80A&B of FIGS. 5A&B, the integrator function has been decomposed into two parallel circuits (i.e., resulting a poyphase decomposition factor of m=2), and the delay operator z represents a half-rate (i.e.,
  (            i      .      e      .        ,                  1        m            ·              f        S              )delay equal to 2/fS, where fS is the effective sample rate of the converter. Circuit 80A is a lowpass modulator with an NTF response that is first-order (i.e., P=1), and circuit 80B is a lowpass modulator with an NTF response that is approximately second-order (i.e., P=2). But rather than decomposing the entire modulator into parallel (polyphase) circuits, in conventional converters the difference function of the modulator (i.e., subtractors 8A&B of circuit 80A&B) and quantization function of the modulator (i.e., quantizers 10A&B in circuits 80A&B) are simply replicated m times and distributed across the m parallel processing paths. See R. Khoini-Poorfard, L. B. Lim, and D. A. Johns, “Time-Interleaved Oversampling A/D Converters: Theory and Practice,” IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, 1997. As discussed in greater detail below, simple replication and distribution of the difference and quantization functions (i.e., rather than polyphase decomposition) causes conventional time-interleaved ΔΣ modulators to exhibit undesirable properties that prevent their use in very high-speed converter applications.
Referring to conventional circuit 80A of FIG. 5A, which utilizes transparent (i.e., unclocked) quantizers with no implicit delay, it can be shown that the quantized output Q(yn) of the modulator is described by the difference equationQ[yn]=Q[xn-1+xn-2−Q(yn-1)−Q(yn-2)+yn-2],where the Q(●) operator represents quantization (rounding). The above difference equation results in a STF(z)=z−1 (i.e., all-pass) and a NTF (z)=1−z−1, where z−1 represents a full-rate delay, equal to one period of the effective sample rate fS. Although the STF and NTF of the time-interleaved ΔΣ modulator are equal to those of the standard (i.e., non-time-interleaved ΔΣ modulator), the output of the circuit is a function of an output Q(yn-1) that has been delayed by only a single full-rate delay (i.e., one sample frequency clock period). Processing of outputs that are delayed by only one period of the effective sample rate fS creates a race condition requiring circuit 80A to operate at a speed of fS=2·fCLK, rather than the intended speed of fCLK. This race condition occurs because the difference and quantization functions of the time-interleaved modulator are not implemented as true polyphase (multirate) operations. A similar race condition occurs in the implementation of circuit 80B, which has an output Q(yn) that is described by the difference equationQ(yn)=Q[xn-2+2·xn-3+xn-4−Q(yn-1−2·Q(yn-2)−Q(yn-3)+2·yn-2−yn-4](i.e., assuming no implicit quantizer delay). Since the output of circuit 80B also depends on an output Q(yn-1) that has been delayed by only one full-rate period, the circuit also must operate at a speed of fS=2·fCLK, rather than the intended speed of fCLK. In addition to the output race condition, circuit 80B exhibits three other undesirable properties: 1) the modulator has a signal transfer function STF(z)=(1+z−1)/(1+z−3) which deviates from a true all-pass response of STF(z)=z−k; 2) the modulator has a noise transfer function NTF(z)=(1−z−1)2(1+z−1)/(1+z−3) which deviates from the desired form of (1−z−1)P for lowpass modulators; and 3) the cascaded integrator structure of the modulator is impractical for use in bandpass converter applications because second-order (bandpass) NTFs of the form (1+ρ·z−1+z−2)P, where −2≦ρ≦+2, cannot be factored as into cascaded first-order functions of the form (1+α·z−1)·(1+β·z−1).
The present inventor has discovered that conventional lowpass ΔΣ converters, as illustrated in FIGS. 2A-C, and conventional bandpass ΔΣ converters, as illustrated in FIG. 3A, have several disadvantages that limit their utility in discrete-to-linear (digital-to-analog) converter applications requiring very high instantaneous bandwidth and high resolution. The present inventor also has discovered that these disadvantages cannot be overcome by: 1) direct adaptations of the conventional parallel processing approaches devised for A/D conversion, as illustrated in FIGS. 4A&B; or 2) by adopting conventional time-interleaved approaches for ΔΣ modulation, as illustrated in FIGS. 5A&B. These disadvantages, which are discussed in greater detail in the Description of the Preferred Embodiment(s) section, include: 1) conversion bandwidth that is limited by the narrow lowpass or narrow bandpass filtering operations used to attenuate shaped quantization noise and errors; 2) conversion resolution (SNDR) that is limited by the clock frequency fCLK of the delta-sigma modulator (i.e., the clock frequency of a two-level quantizer); and 3) conversion resolution that is limited by the low-order noise-shaped response (i.e., generally second-order for bandpass modulators) needed for stable operation with two-level quantizers. In addition, conventional oversampling digital-to-analog converters cannot be operated in parallel as hybrid filter banks (i.e., HFB scheme) or multi-band arrays (i.e., MBΔΣ scheme), without suffering from the amplitude and group delay distortion introduced by imperfect analog filter banks, and/or the nonlinear (intermodulation) distortion introduced by upconverting analog mixers. Because of these disadvantages, the resolution of conventional oversampling converters cannot be increased without: 1) reducing bandwidth to improve the quantization noise attenuation of the output (smoothing) filters; or 2) increasing the converter sample rate by using digital circuits with higher switching speeds, since high-order modulators are unstable with two-level quantization. In addition, conventional oversampling converters employ delta-sigma modulator structures that do not provide a means of dynamically varying, or re-programming, the frequency (fnotch) at which the quantization noise frequency response is a minimum. However, the present inventor has discovered that such a feature can be advantageous in multi-mode applications (e.g., frequency synthesizers and tunable radios) where, depending on its programming, a single converter preferably can operate on different (multiple) frequency bands.